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Úvod > Výpis produktů > F50P - 3U CompactPCI® PlusIO MPC8548 CPU Board
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F50P - 3U CompactPCI® PlusIO MPC8548 CPU Board

3U CompactPCI PlusIO The F50P is a versatile, rugged MPC8548/MPC8543 PowerPC CPU board in 3U CompactPCI PlusIO format for embedded applications

Petr Chalupa

Petr Chalupa

Odolné PC, Military, TEMPEST, Doprava +420 251 614 073
Poptat řešení
Základní informace Specifikace Volitelné Blokové schéma Fotogalerie Ke stažení

Základní informace

Main Features

  • 32-bit CompactPCI and PICMG 2.30 PlusIO
  • 8 HP or 12 HP with front I/O
  • MPC8548 (or MPC8543), up to 1.5 GHz
  • Up to 2 GB (ECC) DDR2 SDRAM
  • Up to 128 KB FRAM, 2 MB SRAM
  • Up to 16 GB SSD Flash
  • Standard front I/O: 2 Gb Ethernet, 2 USB
  • Standard rear I/O: 4 USB, 2 SATA
  • FPGA for user-defined I/O functions (option)
  • MENMON BIOS for PowerPC cards
  • -40 to +70C (8 HP) (screene

Specifikace

CPU
PowerPC PowerQUICC III MPC8548, MPC8548E, MPC8543 or MPC8543E
  • 800 MHz up to 1.5 GHz
  • Please see Standard Configurations for available standard versions.
  • e500 PowerPC core with MMU and double-precision embedded scalar and vector floating-point APU
  • Integrated Northbridge and Southbridge
Memory
  • 2 x 32 KB L1 data and instruction cache, 512 KB / 256 KB L2 cache integrated in MPC8548/MPC8543
  • Up to 2 GB SDRAM system memory
    • Soldered
    • DDR2 with or without ECC
    • Up to 300 MHz memory bus frequency, depending on CPU
  • Up to 16 GB soldered Flash disk (SSD solid state disk)
  • Up to 32 MB additional DDR2 SDRAM, FPGA-controlled, e.g. for video data
  • 16 MB boot Flash
  • 2 MB non-volatile SRAM
    • With GoldCap backup
  • 128 KB non-volatile FRAM
  • Serial EEPROM 4 kbits for factory settings
Mass Storage
Graphics
  • FPGA-controlled (optional)
  • VGA connector prepared at front panel
I/O
  • USB (host)
    • Five USB 2.0 host ports
    • One series A connector at front panel
    • Four ports via rear I/O J2
    • OHCI and EHCI implementation
    • Data rates up to 480 Mbit/s
  • USB (client)
    • One USB client port on series A connector at front panel
    • Via UART-to-USB converter
    • Data rates up to 115.2 kbit/s
    • 16-byte transmit/receive buffer
    • Handshake lines: none
  • Ethernet
    • Up to three 10/100/1000Base-T Ethernet channels with MPC8548/E (two channels with MPC8543/E)
    • Two RJ45 connectors at front panel
    • Two front-panel LEDs for channels for LAN link, activity status and connection speed
    • All three possible also via rear I/O J2 (Note: requires additional Ethernet transformers on rear I/O board or backplane.)
    • See interface configuration matrix showing possible I/O combinations (PDF)
  • User-defined I/O
Front Connections (Standard)
  • One USB 2.0 host (Series A)
  • One USB client (Series A)
  • Two Ethernet (RJ45)
Rear I/O
FPGA
  • The FPGA offers the possibility to add customized I/O functionality. See Options
  • Standard: FPGA not assembled
Miscellaneous
  • Real-time clock with GoldCap backup
  • Temperature sensor, power supervision and watchdog
  • Status LED at the front
  • Reset button
CompactPCI Bus
  • Compliance with CompactPCI Core Specification PICMG 2.0 R3.0
  • System slot
  • 32-bit/32-MHz PCIe-to-PCI bridge
  • V(I/O): +3.3 V (+5 V tolerant)
Busless Operation
  • Board can be supplied with +5 V, +3.3 V and +12 V from backplane, all other voltages are generated on the board
  • Backplane J1 connector used only for power supply
Electrical Specifications
Supply voltage/power consumption:
  • +5 V (-3%/+5%), 800 mA approx.
  • +3.3 V (-3%/+5%), 350 mA approx.
  • ±12 V (-5%/+5%), 1 A approx.
Mechanical Specifications
  • Dimensions: conforming to CompactPCI specification for 3U boards
  • Front panel:
    • 8 HP without FPGA
    • 12 HP with FPGA
  • Weight: 626 g
Environmental Specifications
  • Temperature range (operation):
  • Temperature range (storage): -40..+85°C
  • Relative humidity (operation): max. 95% non-condensing
  • Relative humidity (storage): max. 95% non-condensing
  • Altitude: -300 m to + 3,000 m
  • Shock: 15 g, 11 ms
  • Bump: 10 g, 16 ms
  • Vibration (sinusoidal): 1 g, 10..150 Hz
  • Conformal coating on request
MTBF
162,822 h @ 40°C according to IEC/TR 62380 (RDF 2000)
Safety
PCB manufactured with a flammability rating of 94V-0 by UL recognized manufacturers
EMC
Tested according to EN 55022 (radio disturbance), IEC1000-4-2 (ESD) and IEC1000-4-4 (burst)
BIOS
MENMON
Software Support

Volitelné

CPU
  • Several PowerQUICC III types with different clock frequencies
  • MPC8548 or MPC8548E
    • 1 GHz, 1.2 GHz, 1.33 GHz or 1.5 GHz
  • MPC8543 or MPC8543E
    • 800 MHz or 1 GHz
Memory
  • System RAM
    • 512 MB, 1 GB or 2 GB
    • With or without ECC
  • Flash Disk
    • 2 GB, 4 GB, 8 GB or 16 GB
    • Please note that the 16 GB Flash disk component only supports a temperature range of 0..+60°C!
  • FRAM
    • 0 KB or 128 KB
  • Additional SDRAM
    • 0 MB or 32 MB
    • With optional FPGA
I/O
FPGA
  • The optional onboard FPGA offers the possibility to implement customized I/O functionality.
  • FPGA Altera Arria GX AGX35C
    • 33,520 logic elements
    • 1,348,416 total memory bits
    • Connected to CPU via PCI Express x1 link
  • Connection
    • Available pin count: 64 pins
    • Functions available via rear I/O J2 connector
  • Please note that the FPGA expands the board's width by 4 HP, to 12 HP!
  • You can find more information under 'FPGA Design'
Cooling concept
Some of these options may only be available for large volumes.
Please ask our sales staff for more information.

Blokové schéma

Fotogalerie

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Ke stažení

Datasheet MEN F50P

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